Impact of Gate-Induced Drain Leakage Current on the Tail Distribution of DRAM Data Retention Time

In this paper we propose a new model for leakage mechanism in tail-mode bits of DRAM data retention characteristics. For main-mode bits, leakage current can be attributed to junction thermal-generation leakage current. For tail-mode bits, it is found for the first time that Gate-Induced Drain Leakage (GIDL) current has a dominant impact. The root cause is electric field enhancement caused by metal precipitates located at the gate-drain overlap region. Introduction Recently, DRAM data retention time has nearly doubled for each generation due to the need for high density, high speed and low power DRAMs. The electric field in memory cells is also becoming stronger and leakage current has been increasing with each generation, resulting in poor retention characteristics. Retention time is projected to be an even more serious problem in future DRAMs. It is well known that there are two regions in DRAM failure-bits versus retention time plot (data retention curve), main and tail distribution. Retention characteristics of DRAM chips are limited by only a few leaky cells that belong to the tail distribution. Therefore finding the cause of anomalous leakage and reducing the number of tail-mode cells are the keys to improving data retention. Many researchers have tried to explain the leakage mechanism in tail-mode bits by modeling the memory cell junction as a simple two terminal pn junction [1-4]. Here, we present a new model based on the three-terminal structure, taking the impact of gate electrode into consideration for the first time. Experiment 0.2μm-rule 64Mbit DRAM test vehicles were used for this experiment. Technologies and bias conditions used in these test chips are summarized in Table 1. Data retention characteristics of the test vehicles are measured with memory tester. Also, two types of test devices were fabricated on the same wafers to measure the memory cell leakage current in three different ways as described in Fig. 1. In each test device, 20K quasi-memory cells are connected in parallel to obtain measurable leakage current. Test device without gate (Fig. 1 (a): Type 1) provides information on junction leakage current that flows from the bottom of the junction. Test device with gate is measured in two different ways. With the gate floating (Fig. 1 (b): Type 2), junction thermal leakage current through drain edge is included. And with the gate at Vg=0V (Fig. 1 (c): Type 3), the actual DRAM bias condition during data retention test, actual and total leakage current through the drain can be obtained. To evaluate the impact of GIDL current on data retention time, gate re-oxidation, p-well boron dose, and LDD phosphorus implantation conditions were varied. Results and Discussions A. Effect of gate re-oxidation condition Gate re-oxidation is performed after gate etching and before LDD ion implantation and subsequent Si3N4 sidewall formation. Data retention curves with different gate reoxidation conditions are shown in Fig. 2, where oxide thickness after re-oxidation is no RTO=RTA<RTO1<RTO2<RTO3. Thicker RTO gives more rounded poly-Si edge. In the main mode, a sample with RTA has the best data retention time (Tret) but it tends to get better as the oxide gets thicker. Figures 2 (b)-2 (d) show memory cell leakage of Type 1-Type 3, respectively. The trend of Tret Table 1. Technologies used in the test vehicle. The bias conditions in the memory cell array are also shown. Memory cell structure Design rule Isolation Gate oxide thickness Gate stack layer Cell contact formation Bit line Capacitor dielectric Capacitor structure Storage capacitance Capacitor Over Bit line 0.2μm Shallow Trench Isolation 9nm WSi/poly/SiO2 Si3N4 Self Aligned Contact WSi/poly ON dielectric HSG cylinder 20fF/cell Supply voltage Substrate voltage Word boost voltage Plate voltage Vdd=1.8V Vsub=-1V Vboost=4.2V Vp=0.9V Vd=0~7V Vg=0V Vb=-1V Type 3 Type 3 Vd=0~9V Type 1 Type 1 Vd=0~9V Vg=Open Type 2 Type 2 Sub. STI Gate (a) (b) (c) Fig. 1. Test device structures used for cell leakage measurement. 20K cells are connected in parallel in each test structure. (a) Type 1: quasi-memory cells with no gate. (b) Type 2: memory cells with gate floating during measurement. (c) Type 3: memory cells with gate biased at 0V. 0-7803-6441-4/00/$10.00 (C) 2000 IEEE measurement is consistent with the trend obtained from Type 3 cell leakage current measurement. At Vd around 1.8V, lower leakage is achieved by adopting thicker oxide although RTA sample has the lowest leakage current. In the tail-mode region, Tret is improved by simply increasing the oxide thickness, which is again in good agreement with the Type 3 leakage measurement at relatively high voltage region (Vd=5V). Leakage measurement results obtained from Type 1 and Type 2 did not agree with the Tret trend (both main and tail mode) in either low or high Vd region. This fact clearly suggests that Tret is strongly influenced by gate bias and it cannot be ignored in modeling the leakage mechanism especially in tailmode bits. Figure 3 (a) shows the typical temperature dependence of Type 3 cell leakage current. In low Vd region (Vd<4V), leakage current strongly depends on temperature. But in high field region, it becomes temperature independent. Activation energy Ea is calculated for each Vd and shown in Fig. 3 (b). Ea in low field region is around 0.60eV, which indicates that junction thermal leakage current (Shockley-Read-Hall SRH current) is responsible for the leakage in this region. At Vd near 7V, Ea becomes below 0.1eV, which indicates the dominance of tunneling process in leakage. Since there is no gate leakage current this drain current is GIDL. In Vd=4-6V region, Ea drastically changes from 0.55 to 0.2eV, typically around 0.4eV at Vd=5V. Pure GIDL current is extracted by subtracting Type 2 leakage current from Type 3 current as shown in Fig. 4. In this Vd region, junction leakage current and GIDL are comparable, which means that Ea in this region is an average of the extreme values. We propose that the tailmode bits have GIDL contribution in this range. Figure 5 (b) shows the Ea obtained from data retention curve (Fig. 5 (a)). To calculate Ea, cumulative bit failure rate of 0.01 is picked for main distribution (Main) and 1E-5 and 1E-6 for tail distribution (Tail1 and Tail2). Ea of main distribution is 0.60eV, which is the same value obtained from Type 3 measurement in low Vd region suggesting that junction leakage current is responsible for this leakage. In the tail distribution region, activation energies at Tail1 and Tail2 are in 0.4-0.5eV range, which is consistent with the Ea obtained from Type 3 measurement in relatively high Vd region (Vd=5V). And Ea of Tail2 is always lower than Tail1’s. Cells having even larger GIDL current (i.e. lower Ea, below 0.2eV) have been eliminated in the screen test. These facts are excellent evidence of this proposed leakage mechanism. B. P-Well Boron (PWB) dose dependence Figure 6 (a) shows data retention characteristics of test chips with different PWB concentration. Significant difference can be seen in tail distribution, and retention time is improved by reducing the PWB concentration although no difference is observed in the main distribution. Type 3 leakage (Fig. 6 (d)) is in good agreement with tail Tret trend while Type 1 and Type 2 measurement did not match the Tret trend (Fig. 6 (b), (c)). This fact again indicates that GIDL is responsible for the anomalous leakage in tail-mode bits. C. Effect of LDD phosphorus implantation 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 Data retention time Tret [a.u.] C um ul at iv e bi t fa ilu re noRTO RTA RTO1 RTO2 RTO3 (a) Oxide thickness after re-oxidation noRTO=RTA<RTO1<RTO2<RTO3 1E-17 1E-16 1E-15 1E-14 1E-13 0 1 2 3 4 5 6 7 8 9 Drain voltage Vd [V] Le ak ag e cu rr en t [A /c el l] noRTO RTA RTO1 RTO2 RTO3 (b) Oxide thickness after re-oxidation noRTO=RTA<RTO1<RTO2<RTO3